EN

AW9543TSR

AW9543 2-Channel I2C-bus Switch With Interrupt and Reset

Product details

Parameters

Channel 2
Addresses 4
Reset
Interrupt
I2C Frequency(kHZ) 400
Temperature -40℃~125℃
Power Supply (Min) (V) 1.65
Power Supply (Max) (V) 5.5
Package (mm) TSSOP-14L

Package | Pins | Size

TSSOP-14L

Features

 1-to-2 bidirectional translating switches  I2C bus and SMBus compatible  Two Active-Low Interrupt Inputs  Active-Low Interrupt Output  Active-Low Reset Input  Two address pins, allowing up to four devices on the I2C bus  Channel selection through an I2C bus, in any combination  Power up with all switch channels deselected  Low RON switches  400kHz I2C interface  Allows voltage-level translation between 1.8V, 2.5V, 3.3V and 5V buses  1.65V~5.5V power supply  5.5V tolerant inputs  No glitch on power up  Supports hot insertion  Low standby current  TSSOP-14L package

Description

The AW9543 is a 2-channel, bidirectional translating switch that can be controlled through the I2C bus. The SCL/SDA upstream pair fans out to 2 downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs (INTN0–INTN1), one for each of the downstream pairs, are provided. One interrupt (INTN) output acts as an AND of the two interrupt inputs. An active-low reset (RESETN) input allows the AW9543 to recover from a situation in which one of the downstream I2C buses is stuck in a low state. Pulling RESETN low resets the I2C state machine and causes all the channels to be deselected as does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC terminal can be used to limit the maximum high voltage, which will be passed by the AW9543. This allows the use of different bus voltages on each pair, so that 1.8V, 2.5V, or 3.3V parts can communicate with 5V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O terminals are 5.5 V tolerant.

Technical documentation

Type
Title
Language
Date
Datasheet DS_AW9543_EN_V1.0 英文   2026-06-16

Design & development

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