EN

AW95124FOR

AW95124 24-Bit Translating I2C and SMBus I/O Expander with Interrupt Output, Reset, and Agile I/O Configuration Registers

Product details

Parameters

Channel 24
Addresses 4
Reset
Constant Current ×
Pull-up
Level Shift
Temperature -40℃~105℃
Power Supply (Min) (V) VCCI: 1.08 VCCP: 1.08
Power Supply (Max) (V) VCCI: 3.6 VCCP: 3.6
Package (mm) FOWLP 2.6X2.6-36B

Package | Pins | Size

FOWLP 2.6X2.6-36B

Features

1. I2C-bus to 24-bit parallel port expander 2. 1MHz I2C interface 3. power supply 1) VCCI: 1.08V~3.6V 2) VCCP: 1.08V~3.6V 4. Allows bidirectional voltage-level translation and GPIO expansion between 1.2V, 1.8V, 2.5V and 3.3V I2C bus and P ports 5. Low standby current consumption of 1.5μA (typical at 3.6V VCCI/VCCP) 6. Interrupts can be specified by level or edge(rising or falling) triggered 7. 3.6V tolerant I/O ports 8. Active LOW reset input (RSTN) 9. I2C software reset call 10. Open-drain active-low interrupt output (INTN) 11. Hardware address pin allows four devices on the same I2C, SMBus bus 12. Noise filter on SCL/SDA inputs 13. Latched outputs with high-current drive capability for directly driving LEDs 14. Operation temperature range: -40°C~105°C 15. Package: 1) AW95124FOR: FOWLP 2.6X2.6-36B 2) AW95124QNR: QFN 5X5-32L

Description

AW95124 device provides general purpose parallel input/output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device can operate with a power supply voltage ranging from 1.08V to 3.6V on the I2C bus side (VCCI) and a power supply voltage ranging from 1.08V to 3.6V on the P port side (VCCP).AW95124 supports 100kHz, 400kHz, and 1MHz I2C clock frequencies. AW95124 has Agile I/O plus ports which include additional features designed to enhance the I/O performance. The additional features are: maskable interrupt, latchable inputs, interrupt status register, programmable output drive strength, programmable pull-up and pull-down resistors, programmable open-drain or push-pull outputs, Interrupts can be specified by level or edge(rising or falling) triggered, and can be cleared individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RSTN pin causes the same reset/initialization to occur without depowering the part. The system master can also accomplish a reset via an I2C command and initialize all registers to their default state.

Technical documentation

Type
Title
Language
Date
Datasheet DS_AW95124_EN_V1.2 英文   2025-07-14
Product Design Guide AW95124_Hardware_Design_Guide 英文   2026-05-18

Design & development

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