Features
特性
内核:
带 FPU 和 DSP 的 32 位 RISC MCU
频率最高可达 56 MHz
84 DMIPS, 1.5DMIPS/MHz
DSP:带除法器的 INT32 ALU
专用指令和独立编程
存储器:
64 KByte Flash 存储器
16 KByte ROM用于 Boot Loader
16 KByte 程序 SRAM
16 KByte 数据 SRAM(其中 8 KB 用于 DSP)
EIS 缓冲区
SPI 主机/从机/监听接口
I3C、I2C 主机/从机接口
从机地址:7'h69(默认)
4 个 16 位通用定时器
3 个 16 位双通道 PWM 定时器
32 位看门狗定时器
3 个 16 位三通道 ADC
3 路 10 位 DAC,用于 PGA 偏置校准
BIAS 输出:
3 路霍尔偏置电流
3 路 TMR 偏置电压源
3 个可编程增益放大器
驱动器:恒流线性驱动器
用于 OIS 和 AF 的 3 路输出,13 位 DAC
默认Imax=±160mA
Imax 最高支持 ±200 mA
支持 PWM,频率范围为 10 kHz~1 MHz
模拟电源: VAVDD = 2.6V to 3.6V,
驱动电源: VVM = 1.5V to 3.6V,
I/O: VIOVDD = 1.2V/1.8V
关断模式功耗低于 12 μA
WLCSP 3.555 mm × 1.255 mm × 0.3 mm - 27B封装
Description
General Description
1.The AW86068 is an optical image stabilization (OIS) controller and driver which also support auto focus driving. It is always used in a camera module of smart mobile phone or other camera equipment.
2.The 32-bit RISC MCU core adopts a Harvard architecture and integrates DSP and FPU. The code bus connects to Flash, ROM, and code SRAM, while the data bus connects to data SRAM and the APB bridge. Operating at 56 MHz, the core delivers up to 84 DMIPS of computing performance for algorithm processing.
3.The AW86068 integrates an on-chip 32-bit CPU as the controller, a flash memory for program and user data, 3 channels per ADC, 3 DACs for calibrating Hall sensor offsets, 3 Hall bias circuits, and 3 H-bridge drivers for OIS and AF.
4.The AW86068 DSP has dedicated ALU hardware that integrates instruction flow control, storage access, scalar operations, matrix operations, and digital filters, specifically designed for algorithm acceleration optimization.
5.There is an SPI I/F module that supports on-chip master, slave, and monitor. One I2C module is available, supporting master/slave mode, and one I3C module supports master/slave mode.