A：在芯片正常的情况，可以按照如下步骤进行排查
步骤一、按键失效时需先确认I2C通信：
（1） VCC供电是否在2.5V~5.5V之内；
（2） RSTN或SHDN使能引脚是否拉高；
（3） I2C地址有AD0和AD1的链接方式决定，通信过程中是否正确；
（4） 通过读0x10寄存器的CHIPID 0x23来判断I2C通信是否成功。
步骤二、确认硬件设计：端口做gpio output时，
（1） PX_X或OUTx端口尽量不要有下拉电阻，防止下拉能力过强导致端口输出高也无法拉高；
（2） AW9523B和AW9527的P1_X端口为Push-Pull输出；P0_X端口默认为Open-Drain输出，也可以通过0x04寄存器的bit4设置为Push-Pull；P0_X作Open-Drain输出时，外部需准备上拉电阻。
步骤三、接着确认寄存器配置
（1） 端口的模式配置：
AW9523B和AW9527的0x12和0x13寄存器如下：
Table 1. LED mode switch register（12H）
|
Address
|
Name
|
Description
|
Default
|
|
12H
|
LED Mode Switch
|
Configure P0_7~P0_0 as LED or GPIO mode。
1：GPIO mode
0：LED mode
|
FFH
|
Table 2. LED mode switch register（13H）
|
Address
|
Name
|
Description
|
Default
|
|
13H
|
LED Mode Switch
|
Configure P1_7~P1_0 as LED or GPIO mode。
1：GPIO mode
0：LED mode
|
FFH
|
AW9110C和AW9106C的0x12和0x13寄存器如下：
Table 3. P0WKMD(12H), GPIO control switch to LED driver register
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:6]
|
-
|
-
|
Remain
|
|
D5
|
P0WKMD[5]
|
OUT9 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D4
|
P0WKMD[4]
|
OUT8 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D3
|
P0WKMD[3]
|
OUT7 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D2
|
P0WKMD[2]
|
OUT6 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D1
|
P0WKMD[1]
|
OUT5 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D0
|
P0WKMD[0]
|
OUT4 mode control
0：LED mode
1：GPIO mode
|
1
|
Table 4. P1WKMD(13H), GPIO control switch to LED driver register
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:4]
|
-
|
-
|
Remain
|
|
D3
|
P1WKMD[3]
|
OUT3 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D2
|
P1WKMD[2]
|
OUT2 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D1
|
P1WKMD[1]
|
OUT1 mode control
0：LED mode
1：GPIO mode
|
1
|
|
D0
|
P1WKMD[0]
|
OUT0 mode control
0：LED mode
1：GPIO mode
|
1
|
（2） 方向配置是否正确：
AW9523B和AW9527的0x04和0x05寄存器如下：
Table 5. Configuration register（04H，05H）
|
Address
|
Name
|
Description
|
Default
|
|
04H
|
Config_Port0
|
P0 port input/output mode select. 0-output; 1-input
|
00H
|
|
05H
|
Config_Port1
|
P1 port input/output mode select. 0-output; 1-input
|
00H
|
AW9110C和AW9106C的0x04和0x05寄存器如下：
Table 6. P0DIR(04H),GPIO input or output select register or as BLINK,SMART-FADE Mode select
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:6]
|
-
|
-
|
Remain
|
|
D5
|
P0DIR[5]
|
OUT9 input or output choice
0：output
1：input
|
0
|
|
D4
|
P0DIR[4]
|
OUT8 input or output choice
0：output
1：input
|
0
|
|
D3
|
P0DIR[3]
|
OUT7 input or output choice
0：output
1：input
|
0
|
|
D2
|
P0DIR[2]
|
OUT6 input or output choice
0：output
1：input
|
0
|
|
D1
|
P0DIR[1]
|
P0WKMD[1]=1, OUT5 input or output choice
0：output
1：input
|
0
|
|
D0
|
P0DIR[0]
|
P0WKMD[0] =1, OUT4 input or output choice
0：output
1：input
|
0
|
Table 7. P1DIR(05H),GPIO input or output selection register, or used for BLINK,SMART-FADE mode choice
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:4]
|
-
|
-
|
Remain
|
|
D3
|
P1DIR[3]
|
P0WKMD[3] =1 , OUT3 input or output choice
0：output
1：input
|
0
|
|
D2
|
P1DIR[2]
|
P0WKMD[2] =1 , OUT2 input or output choice
0：output
1：input
|
0
|
|
D1
|
P1DIR[1]
|
P0WKMD[1] =1 , OUT1 input or output choice
0：output
1：input
|
0
|
|
D0
|
P1DIR[0]
|
P0WKMD[0] =1 , OUT0 input or output choice
0：output
1：input
|
0
|
（3） 输出电平：
AW9523B和AW9527的0x02和0x03寄存器如下
Table 8. Output state register（02H，03H）
|
Address
|
Name
|
Description
|
Default
|
|
02H
|
Output_Port0
|
Set P0 port output value. 0-low level; 1-high level
|
Refer to table1
|
|
03H
|
Output_Port1
|
Set P1 port output value. 0-low level; 1-high level
|
Refer to table1
|
AW9110C和AW9106C的0x02和0x03寄存器如下：
Table 9. P0DO(02H),GPIO output state register or as driver control in SMART-FADE mode
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:6]
|
-
|
-
|
Remain
|
|
D5
|
P0DO[5]
|
OUT9 pin state
0：Low level
1：High level
|
Depend on AD0 and AD1
|
|
D4
|
P0DO[4]
|
OUT8 pin state
0：Low level
1：High level
|
|
D3
|
P0DO[3]
|
OUT7 pin state
0：Low level
1：High level
|
|
D2
|
P0DO[2]
|
OUT6 pin state
0：Low level
1：High level
|
|
D1
|
P0DO[1]
|
P0WKMD[1]=1,as driving OUT5 pin state
0：Low level
1：High level
|
|
D0
|
P0DO[0]
|
P0WKMD[0]=1,as driving OUT4 pin state
0：Low level
1：High level
|
Table 10. P1DO(03H),GPIO output state register or as driver control in SMART-FADE mode
|
Bit
|
Symbol
|
Description
|
Default
|
|
D[7:4]
|
-
|
-
|
Remain
|
|
D3
|
P1DO[3]
|
P1WKMD[3]=1,as driving OUT3 pin state
0：Low level
1：High level
|
Depend on AD0 and AD1
|
|
D2
|
P1DO[2]
|
P1WKMD[2]=1,as driving OUT2 pin state
0：Low level
1：High level
|
|
D1
|
P1DO[1]
|
P1WKMD[1]=1,as driving OUT1 pin state
0：Low level
1：High level
|
|
D0
|
P1DO[0]
|
P1WKMD[0]=1,as driving OUT0 pin state
0：Low level
1：High level
|
步骤四、用示波器测试PX_X或OUTx端口信号，看是否上述第三步设置
注意：
当VCC上电且RSTN或SHDN拉高后，PX_X或OUTx端口的电平默认状态和AD1、AD0的关系如下：
AW9523B和AW9527默认输出电平：
|
AD1
|
AD0
|
P1_7
|
P1_6
|
P1_5
|
P1_4
|
P1_3
|
P1_2
|
P1_1
|
P1_0
|
P0_7
|
P0_6
|
P0_5
|
P0_4
|
P0_3
|
P0_2
|
P0_1
|
P0_0
|
|
GND
|
GND
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
|
GND
|
VBAT
|
0
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
0
|
0
|
0
|
0
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
|
VBAT
|
GND
|
1
|
1
|
1
|
1
|
0
|
0
|
0
|
0
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
0
|
0
|
0
|
0
|
|
VBAT
|
VBAT
|
1
|
1
|
1
|
1
|
1
|
1
|
1
|
1
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
AW9110C和AW9106C默认输出电平：
|
AD1
|
AD0
|
OUT9
|
OUT8
|
OUT7
|
OUT6
|
OUT5
|
OUT4
|
OUT3
|
OUT2
|
OUT1
|
OUT0
|
|
GND
|
GND
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
|
GND
|
VCC
|
0
|
0
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
1
|
1
|
1
|
1
|
|
VCC
|
GND
|
Hi-Z
|
Hi-Z
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
|
VCC
|
VCC
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
Hi-Z
|
1
|
1
|
1
|
1
|
