| Core | M0+ |
| fₘₐₓ(MHz) | 48 |
| Flash(KB) | 32 |
| RAM(KB) | 2 |
| Dataflash(KB) | - |
| I/O | 18 |
| DIV | - |
| DMA | - |
| CRC | Y |
| Adv Timer | - |
| GP Timer | 1 |
| Ba Timer | 2 |
| LP Timer | 1 |
| WDG | 1*IWDG, 1*WWDG |
| RTC | - |
| U(S)ART | 1 |
| LP UART | 1 |
| I2C | 1 |
| I3C(Slave/Master) | - |
| SPI | 1 |
| I2S | Y |
| USB2.0 | - |
| CAN2.0B | - |
| LIN | - |
| ADC(ch、bit、Msps) | 1*(9、12、1) |
| DAC | - |
| COMP | 1 |
| OPA | 2 |
| PGA | - |
| VS | - |
| IEXC | - |
| CAP | - |
| Segment LCD | - |
| LED/RGB | - |
| Package | QFN20 |
| Package Size | 3x3 |
| VDD(V) | 1.8~5.5 |
| Temp(℃) | -40~85 |
| Special Features | 96-bit UID, low power modes |
| QFN 3X3-20L |

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유형
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제목
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언어
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날짜 | |||
|---|---|---|---|---|---|---|
| Datasheet | DS_AW32L002_EN_V1.0 | 英文 | 2025-11-11 | |||
| Product Design Guide | AW32L002 Software Design Guide | 中文 | 2025-11-25 | |||
| Product Design Guide | AW32L002 Hardware Design Guide | 中文 | 2026-02-26 |