EN

AW32L002QNR

제품 상세 정보

매개변수

Core M0+
fₘₐₓ(MHz) 48
Flash(KB) 32
RAM(KB) 2
Dataflash(KB) -
I/O 18
DIV -
DMA -
CRC Y
Adv Timer -
GP Timer 1
Ba Timer 2
LP Timer 1
WDG 1*IWDG, 1*WWDG
RTC -
U(S)ART 1
LP UART 1
I2C 1
I3C(Slave/Master) -
SPI 1
I2S Y
USB2.0 -
CAN2.0B -
LIN -
ADC(ch、bit、Msps) 1*(9、12、1)
DAC -
COMP 1
OPA 2
PGA -
VS -
IEXC -
CAP -
Segment LCD -
LED/RGB -
Package QFN20
Package Size 3x3
VDD(V) 1.8~5.5
Temp(℃) -40~85
Special Features 96-bit UID, low power modes

패키지 | 핀 | 크기

QFN 3X3-20L

특징

1, Core and system 1.1, 32-bit MCU 1.2, Frequency up to 48MHz 2, Up to 32KB Flash and up to 2KB SRAM 3, Clock, reset and power management 3.1, POR, PDR, PVD 3.2, Built-in 8MHz HSI 3.3, Built-in 32.768KHz LSI 3.4, PLL for CPU clock 4, Low Power Run mode, Sleep mode, Low Power Sleep mode, Stop mode, Deep Stop mode and Standby mode 5, Total 7 timers: 5.1, One 16-bit general purpose timer (TIM3) 5.2, Two 16-bit basic timers (TIM16 / TIM17) 5.3, One 16-bit low power timer (LPTIM) 5.4, Two watchdog timers (IWDG and WWDG) 5.5, One 24-bit Systick timer 6, Up to 18 fast I/O ports: 7, Up to 4 communication interfaces: One UART, One LPUART, One I2C, One SPI (support I2S mode) 8, One 12-bit Analog-digital-converter (ADC) 9, One analog comparator 10, Two operational amplifiers 11, Embedded CRC engine 12, 96bit chip unique ID (UID) 13, Debug mode: Serial-debug-interface (SWD) 14, Working temperature range is -40°C ~ 85°C 15, Working supply range is 1.8V ~ 5.5V, where Standby mode is not supported from 1.8V to 2.0V 16, Available in TSSOP20 package

기술 문서

유형
제목
언어
날짜
Datasheet DS_AW32L002_EN_V1.0 英文   2025-11-11
Product Design Guide AW32L002 Software Design Guide 中文   2025-11-25
Product Design Guide AW32L002 Hardware Design Guide 中文   2026-02-26

설계 및 개발

추가 조건이나 필요한 리소스가 있는 경우, 아래 제목을 클릭하여 사용 가능한 경우 상세 페이지를 확인하세요.