| Actuator Type |
SOC-OIS |
| Output I(mA) |
±160mA |
| VDD (Max) (V) |
3.6 |
| VDD (Min) (V) |
2.6 |
| I2C (Hz) |
100K
400K
1M |
| I2C Addr |
Configurable |
| IQ (mA) |
5 |
| ISD (μA) |
12 |
| Temperature |
-40℃~85℃ |
| Control Mode |
/ |
| ADC (bit) |
16 |
| Package (mm) |
WLCSP 3.555X1.255-27B |
Features
Core:
♦ ARM 32-bit STARCU with FPU and DSP
♦ Frequency up to 48MHz
♦ 72 DMIPS, 1.5DMIPS/MHz
DSP:
♦ INT32 ALU with divider
♦ Private instruction and independent programing
Memories:
♦ 64KByte Flash Memory
♦ 16KByte ROM for boot loader
♦ 16KByte Program SRAM
♦ 16KByte Data SRAM(8KB for DSP)
EIS buffer
SPI Master/Slaver/Monitor I/F
I3C, I2C Master/Slaver I/F
♦ Slaver address: 7’h69(Default)
4x 16bit General Timers
3x 16bit PWM Timers with 2-ch each
32-bit Watch Dog Timer
2x 16-bit AD Converter with 3-ch each
10-bit DA Converter for PGA offset, Output 2-ch
BIAS output:
♦ Hall Bias current sink, 2-ch
♦ TMR Bias voltage source, 2-ch
2 Programmable Gain Amplifiers
Driver:
♦ Constant Current Linear Driver
♦ Output 3-ch for OIS and AF, 13-bit DAC
♦ Default Imax=±160mA,Imax can support ±200mA.
♦ PWM supported, PWM frequency 10K~1MHz
Shutdown mode with consumption less than 12uA
WLCSP 3.555mm × 1.255mm × 0.3mm - 27B package
General Description
1.The AW86066 is an optical image stabilization (OIS) controller and driver which also support auto focus driving. It is always used in a camera module of smart mobile phone or other camera equipment.
2.The STARCU is Harvard structure and has own DSP and FPU. The bus for code connects flash, ROM and code SRAM and the bus for data connects data SRAM and APB bridge. With the 48MHz clock, STARCU can provide 72DMIPS computing power for algorithm.
3.The AW86066 integrates an on-chip 32-bit CPU as the controller, a flash memory for program and user data, 3 channels per ADC, 2 DACs for calibrating Hall sensor offsets, 2 Hall bias circuits, and 3 H-bridge drivers for OIS and AF.
4.The AW86066 DSP has dedicated ALU hardware that integrates instruction flow control, storage access, scalar operations, matrix operations, and digital filters, specifically designed for algorithm acceleration optimization.
5.There is an SPI I/F module that supports on-chip master, slave, and monitor. One I2C module is available, supporting master/slave mode, and one I3C module supports master/slave mode.
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